This invention relates generally to semiconductor memory devices for storing digital data and more particularly to an adaptive or fault tolerant full wafer nonvolatile digital memory having an array of identical self controlled sites containing both memory and logic circuitry.
The manufacture of wafer scale integrated circuits is well known in the art. Typically the wafer contains additional circuit elements which can be switched into place to replace circuits which are faulty because of defects in the material or defects inducted as a result of manufacture. The switching process or procedure may involve fabrication of special connecting or disconnecting features by metal depositions, ion implants, laser cutting, or laser fusing. Alternatively, the switching can be accomplished by using conventional circuit elements such as transistors which can be programmed to form a desired end circuit configuration.
The use of wafer scale circuits often also involves redundancy for the purpose of working around faults which may occur while the circuit is installed in a system. Here the switching processes or procedures almost always rely on the use of conventional circuit elements such as transistors.
In the narrower area of systolic array technology, the concept of an array of identical processors communicating with nearest neighbor processors has also evolved. The capability of switching the links to nearest neighbors has been actively studied for the purpose of switching out of the array any faulty processors and the concept of forming electrical circuit links between identical circuits arranged in an array has also been used as a defect avoidance scheme to manufacture wafer scale dynamic memory. However, individual memory sites are connected together in a permanently fixed spiral to form a large serial memory.
It is an object of the present invention, therefore, to provide an improvement in fault tolerant semiconductor circuitry.
It is another object of the present invention to provide an improvement in large semiconductor memory devices by providing a fault tolerant block oriented random access addressing and switching capability which can be used for avoidance of material and process inducted defects.
It is a further object of the invention to provide a large semiconductor memory device capable of tolerating circuit failures in the field by providing a flexibility of the block oriented random access addressing and switching capability.